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| Peripheral Imaging Corporation PI0256HSN, PI0512HSN, PI1024HSN 25-m-Pitch Wide Aperture Spectroscopic Photodiode Arrays Engineering Data Sheet Description Peripheral Imaging Corporation's HSN series is family of self-scanning photodiode solid-state linear imaging arrays. These photodiode sensors employ PIC's proprietary CMOS Image Sensing Technology to integrate the sensors into a single monolithic chip. These sensors are optimally designed for applications in spectroscopy. Accordingly, these sensors contain a linear array of photodiodes with an optimized geometrical aspect ratio (25-m aperture pitch x 2500-m aperture width) for helping to maintain mechanical stability in spectroscopic instruments and for providing a large light-capturing ability. The family of sensors consists of photodiode arrays of various lengths, 256, 512, and 1024 pixels. The HSN photodiode arrays are mounted in 22-pin ceramic side-brazed dual-in-line packages that fit in standard DIP sockets. A diagram of its pinout configuration is seen in Figure 1. VSS VDD ABG ADDCAP TD1 VSS TD2 NC NC NC ABD 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 NC VSS START CLK NC VDD EOS NC VSS QOUT VDD Features * * * * * * * * * * * Selectable saturation charge capacities. 65-pC capacity for wider dynamic range. 25-pC for lower noise readout. Wide spectral response (180 - 1000 nm) for UV and IR response. NP junction photodiodes with superior resistance to UV damage. Low dark current. Integration time up to 11 seconds at room te mperature. Integration time extended to hours by cooling. Anti-blooming circuitry. High linearity. Low power dissipation (less than 1 mW). Geometrical structure for enhanced stability and registration. Standard 22-lead dual-in-line IC package. Figure 1. Pinout configuration. Sensor Characteristics The Peripheral Imaging Corporation's self-scanned HSN photodiodes are spaced on a 25-m pitch. The line density is 40 diodes/mm and accordingly the overall die lengths of the different arrays vary with the number of photodiodes. For example, the 256-pixel array is 6.4-mm long, the 512-pixel array is 12.8-mm long, and the 1024-pixel array is 25.6-mm long. Each array has four additional dummy photodiodes. On each side, there are one dark (non-imaging) dummy photodiode and one imaging dummy photodiode. The height of the sensors is 2500 m. The tall, narrow apertures make these sensors desirable for use in monochromators and spectrographs. Page 1 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet 2 Dummy Pixels 25m Active Pixels 2 Dummy Pixels 2500m Figure2. Geometry and layout of photodiode pixels. During normal operation, the photons incident in or near the NP photodiode junction generate free charges that are collected and stored on the junction's depletion capacitance. The number of collected charges is proportional to the light exposure. Figure 3 shows the stored signal charge as function of light exposure at a wavelength of 575 nm. The exposure is the product of 2 the light intensity in nW/cm and integration time in seconds. The charge accumulates linearly until reaching the saturation charge, and the corresponding exposure is the saturation exposure. There are two saturation limits which are described in the Selectable Charge Capacity section below. The responsivity may be calculated as the saturation charge divided by saturation exposure. The predicted -4 2 typical responsivity of a photodiode is 1.5x10 C/J/cm at 575 nm. Figure 4 shows the predicted responsivity of the photodiodes as a function of wavelength. 80 Output Charge (pC) 70 60 50 40 30 20 10 0 0 100 saturation with cap saturation w/o cap 200 300 400 500 Exposure (nJ/cm 2) Figure 3. Stored signal charge as function of exposure at a wavelength of 575 nm. Page 2 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet 2.5E-04 QE=80% Responsivity (C/J/cm) 2.0E-04 1.5E-04 1.0E-04 5.0E-05 0.0E+00 100 QE=60% QE=40% QE=20% capacitors are connected. When ADDCAP is low, all the capacitors are disconnected. It is advised that all the photodiodes are reset after each toggle of ADDCAP. This is simply done by clocking one linescan of the photodiode array. Anti-Blooming Circuit Each photodiode pixel has a built-in anti-blooming circuit structure. Without an anti-blooming circuit, it is possible that a fraction of the excess charge from one pixel will flow into neighboring pixels. The antiblooming circuit prevents this by redirecting the excess current into the anti-blooming drain before the photodiode is too full. A self-biased anti-blooming gate sets the level at which the charge begins to flow into the drain. Think of it this way. If the photodiode were your bathroom sink, then the anti-blooming circuit would be your sink's overflow drain. The anti-blooming circuit may be disabled by grounding the anti-blooming gate. This would in effect raise the drain level. 300 500 700 900 Wavelength (nm) Figure 4. Predicted spectral response. The Quantum Efficiency (QE) can be calculated by dividing the responsivity by the area of the sensor's element and multiplying the resulting ratio by the energy per photon in electron volts (eV). The dark current is typically 0.2 pA at 25C and varies as function of temperature. The dark current will contribute dark-signal charges and these charges will increase linearly with integration time. The dark signal and the photo-generated signal combined result in the total signal charge. Self-Scanning Circuit Figure 5 shows a simplified electrically equivalent circuit diagram of the photodiode array. An MOS read switch connects every photodiode in the array to a common output video line. Incident photons generate electron charge that is collected on each imaging photodiode while the switch is open. The shift register is activated by the start pulse. A pulse propagates through each shift register stage and activates the MOS read switches sequentially. As the shift register sequentially closes each read switch, the negative stored charge, which is proportional in amount to the light exposure, from the corresponding photodiode is readout onto the video line, QOUT. Typically, an external charge-integrating amplifier senses the negative output charge on the video line from each photodiode pixel. The shift register continues scanning the photodiodes in sequence, until the last shift register stage is reach, at which time the fourth and last dummy pixel is read out and end-of-scan (EOS) output is held high for one clock cycle. The next start pulse can then restart the shift register. Selectable Charge Capacity The HSN devices have the unique feature of having a selectable charge capacity. There is a bank of capacitors with one capacitor for each photodiode pixel. When the capacitors are connected to the photodiodes, they give the photodiodes a charge capacity of typically 65 pC. This large charge capacity is useful in applications that demand high dynamic range and high signal-to-noise ratios. With the capacitors disconnected, the photodiodes have an intrinsic charge capacity of typically 25 pC. With a reduced capacitance, the photodiode array can operate with a lower reset (kTC) noise. The ADDCAP pin is provided to control the connection of the capacitors. When ADDCAP is high, all the Page 3 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet CLK ART SHIFT REGISTER EOS QOUT TD1 TD2 Dummy 3 Dummy 1 Dummy 2 VSS Figure 5. Simplified circuit diagram of a HSN photodiode array. The diagram does not include the capacitor bank and the anti-blooming circuitry. I/O Pins Besides the VSS and VDD supply pins, there are 9 functionally active I/O pins. Only two clocks, CLK and START, are required for controlling the timing of the sensor's video readout. One additional digital input, ADDCAP controls the bank of capacitors as described in the Selectable Charge Capacity section above. The digital output, EOS, marks the end of the line-scan. The charge output pin, QOUT, is typically connected to a charge-integrating amplifier that is biased to Vbias (see Recommended Operating Conditions section below). For normal anti-blooming operation, the ABG requires a 0.1-F capacitor connected to VSS and the ABD is also biased to Vbias. Each temperature diode is operated with a small constant current that forwardbiases its PN junction. By measuring the forward-bias voltage, one can track the silicon die temperature. The temperature diodes may be disabled by connecting their anodes to VSS. These I/Os are listed with their acronym designators and functional descriptions in the following Table 1. Table 1. Symbols and functions and I/O pins. Symbol VSS VDD START CLK ADDCAP EOS QOUT ABG ABD TD1 TD2 NC Function and Description Ground. +5.0 Volts. Start Pulse: Input to start the line scan. Clock Pulse: Input to clock the shift register. Add Capacitors: Input that selects the bank of capacitors to increase charge capacity. End Of Scan: Output from the shift register to indicate the completion of one line scan. Video Charge Output: Output from the photodiodes pixels. Anti-Blooming Gate: Self-biased gate for setting anti-blooming level. Requires 0.1-F connected to VSS. Anti-Blooming Drain: Bias for anti-blooming drain. Set to Vbias. Temperature Diode 1: Anode of temperature diode 1. Temperature Diode 2: Anode of temperature diode 2. No Connection Dummy 4 Pixel n-1 Pixel 1 Pixel 2 Pixel n Page 4 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Clock and Voltage Requirements The clocking requirements are relatively simple. As it was indicated in Figure 5 and Table 1, there are only two input signals that require clocked inputs. They are CLK, the clock for the shift register, and START, the to CLK tds tdh START tsh tsd QOUT Dummy Pixel 1 (Dark) Dummy Pixel 2 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel n-1 Pixel n Dummy Pixel 5 (Dark) Dummy Pixel 6 (Dark) shift register start pulse. The timing specifications and the symbol definition for Figure 6 are listed in Table 2. The control clock amplitudes for I/Os are compatible with the 5-Volt CMOS devices. twl twh tds tdh tsch EOS telh tehl Figure 6. Timing diagram. Table 2. Symbol definitions and timing specifications for timing diagram. Item Clock cycle time Clock high pulse width Clock low pulse width Clock duty cycle Data setup time Data hold time EOS low-to-high delay EOS high-to-low delay Signal delay time Signal settling time Signal settle to clock edge Symbol to twh twl tds tdh telh tehl tsd tsh tsch Min 1000 900 100 1 100 100 Typical 10000 Max 50 99 400 400 50 900 0 Units ns ns ns % ns ns ns ns ns ns ns Page 5 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Recommended Operating Conditions The following table lists the recommended operating conditions. Table 3. Recommended operating conditions at 25 C. Parameters Power supply Input clock pulses high level 1 Input clock pulse low level 1 Video charge output external bias Clock frequency Integration time 2 Symbol VDD Vih Vil Vbias Fclk Tint Min 4.5 VDD - 0.8 0.0 VDD - 0.5 0.26 (256HSN) 0.52 (512HSN) 1.03 (1024HSN) Typical 5.0 VDD 0.0 VDD - 0.5 0.1 Max 5.5 VDD 0.8 VDD 1.0 11000 (w/ cap) Units Volts Volts Volts Volts MHz ms Notes: 1. Applies to all control-clock inputs. 2. Integration time is specified at room temperature such that the maximum dark current charge build up in each pixel is less than 10% of the minimum saturation charge. Accordingly, it may be as long as 11 seconds at room temperature with the added capacitors. Longer integration times may be achieved by cooling the device. An appropriate clock frequency must be chosen so that the shift register completes its operation within the desired integration time. Page 6 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Electro-Optical Characteristics The following table lists the electro-optical characteristics. Table 4. Electro-optical characteristics at 25C. Parameters Center-to-center spacing Aperture width Pixel area Fill factor 1 Quantum efficiency 1,2 Responsivity 1,2 Nonuniformity of response 3 Saturation exposure 2 Saturation charge 4 Average dark current 5 Spectral response peak Spectral response range 6 Symbol A FF QE R Esat Qsat Typical 25 2500 6.25x10 -4 72 70 1.5x10 -4 2 370 (w/ cap) 430 (w/ cap) 130 (w/o cap) 170 (w/o cap) 65 (w/ cap) 55 (w/ cap) 20 (w/o cap) 25 (w/o cap) 0.2 600 180 - 1000 Min Max 5 Units m m cm2 % % C/J/cm2 +/-% nJ/cm2 pC 0.5 pA nm nm Notes: . . . 1. Fill factor, quantum efficiency, and responsivity are related by the equation R = (qe/hc) QE FF A, where qe is the charge of an electron and hc/ is the energy of a photon at a given wavelength. Responsivity is therefore given per pixel. 2. At wavelength of 575 nm (yellow-green) and with no window. 3. Measured at 50% Vsat with an incandescent tungsten lamp filtered with an Schott KG-1 heat-absorbing filter. 4. Saturation charge specified for a video output bias of 4.5 volts. o 5. Max dark leakage 1.5 x average dark leakage measured with an integration period of 500 ms at 25 C. 6. From 250-1000 nm, responsivity 20% of its peak value. Page 7 of 8 March 13, 2002 PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Package Dimensions The following figure provides the package dimensions. B 0.080+/-0.008 0.148 +/-0.010 0.394+/-0.010 Sensing Area 2.5 mm Silicon Chip Pin 1 A 0.148 +/-0.010 0.054+/-0.006 0.026+/-0.006 0.100+/-0.005 1.00+/-0.005 Device PI0256HSN PI0512HSN PI01024HSN A 1.0800.010 1.0800.010 1.6000.010 B 6.4 mm 12.8 mm 25.6 mm Figure 7. Package dimensions. Note: Dimensions are in inches except where millimeters (mm) are indicated. (c)2001-2002 AMI Semiconductor. Printed in USA. All rights reserved. Specifications are subject to change without notice. Contents may not be reproduced in whole or in part without the express prior written permission of AMIS. Information furnished herein is believed to be accurate and reliable. However, no responsibility is assumed by AMIS for its use nor for any infringement of patents or other rights granted by implication or otherwise under any patent or patent rights of AMIS. AMI Semiconductor, Inc. 650 N. Mary Ave. * Sunnyvale * CA 95085 Page 8 of 8 www.amis.com 408-962-1913 March 13, 2002 0.400+/-0.010 [AT STAND OFF] |
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